Yesterday we discovered that the reference A13 schematic we got have some mouse traps inside.
The DDR3 RAM ball assignments are shifted with +1, this means if A0 address signal is assigned as K3 on Hynix datasheet it’s labeled K4 on A13 “reference” design schematic.
I still don’t know if this is intentional or not.
As explained on this tread http://lists.phcomp.co.uk/pipermail/arm-netbook/2012-March/002881.html the factories in China which produce electronic devices have no or little R&D, they rely on the SoC manufacturer to provide them with chips, schematics, reference PCB layout and everything they need just to start production, so they just pay for the design to “solution companies” and do what they can best – assembly cheap devices.
There may be other traps as well, but this will not stop us to complete our schematic, my great worries now are if the processor pin assignments are correct in the A13 datasheet🙂 as we have nothing to compare with.
I already ordered one A13 tablet from China as these are still not available on ebay, so we will be able to do some reverse engineering and track if all ports on the A13 are defined correctly but this will delay a bit the project.
Hopefully I will got the A13 tablet next week and will tear it on parts, then post my findings here🙂
I already wrote note in the GitHub A13-PDF readme.txt about this problem with the schematic so other people who watch this project beware.