FOSDEM was great place to present the TERES I, as there were the right people who share open source values.
We got lot of people passing through our table and got tons of feedback and suggestions. Thanks guys!
One of the most asked questions was: “can you make it with more RAM memory?” The answer is yes, we can and we even have the memory chips which easily allow TERES I to be with 2GB RAM, but these are quite expensive than the mainstream memories as they are just two 4Gb memory chips put in one package with two Chip Select signals which A64 supports. As these memories are not so used their prices is more than double of the normal DDR memory price and this is why we though initially that this will be expensive option to consider. If we put 8Gb DDR memories on TERES I instead of 4Gb and make the RAM memory 2GB this will affect the price with EUR 15. Perhaps we should just add this as option when we assembly the main boards and people can decide what to buy 1GB or 2GB RAM version.
The 4GB mainboard eMMC flash is also quite humble for storage. Micron who manufacture this eMMC has also 16GB and 32GB versions, but they are very slow to deal with, just to receive quotation from their sale reps here needs weeks and even if you order they will tell you something like 20-30 weeks delivery time. For the moment this is no go. We use these 4GB eMMC in our other boards this is why we decided to use here too. The 4GB eMMC is in stock and we can produce right now. The micro SD card connector kinda solves the storage issue as you can use up to 128GB micro SD cards, but they are not so fast as the eMMC on board. Anyway if we could make deal with Micron later we could offer mainboards with more on board eMMC.
Another interesting suggestion was to add small SPI flash on the mother board. Initially as hardware guys we decided to not do this when we designed the main board. our though was: if you have eMMC 4GB on board which you can read with 100MB/s and write with 10MB/s why would you need slow serial SPI flash with small capacity like 4MB on board? We got explanation at FOSDEM why some people would love to have it. The SPI Flash could be used to have boot code from which A64 will always boot first. The SPI Flash could be hardware write protected, i.e. you will be always sure that your processor boots trusted software and no one could overwrite it except if he has physical access to your laptop and open the plastic and put the SPI to read/write mode again. The mainboard eMMC could be overwritten from user space, so considered as compromised media for secure boot by the people who care about their security.
One more good feedback was that A64 has OTP bits, one of which once set A64 will refuse to boot unsigned code, and no one knows how to sign code for A64 yet, so this effectively bricks your device and all existing A64 boards and tablets and laptops suffer from this problem. One could now write malicious software which to set this OTP bit and brick the A64 devices on the market. Fortunately there is A64 pin which enables and diables the OTP writting at hardware level, so we are going to disable OTP write by hardware.
Another question was “can I have better display with higher resolution?” Sure you can! TERES1 laptop has eDP interface which all laptop LCDs share, so any LCD with eDP interface will work, and of course will require proper Linux setting. Right now if you do not like the current 1366×768 resolution you can search for other 11.6″ with eDP connector and spend almost as the cost of the TERES I for LCD with IPS and 2K or 3K resolution, but franky we do not see the point of fancy graphics as TERES I would never be laptop for graphics developers anyway.
Other people were asking: “can I have 16GB of RAM, SSD disk” No, unfortunately this is not possible. A64 is humble low cost processor, it has no SATA, so SSDs are not possible to connect except via USB which spoils the SATA speed. And IIRC 4GB RAM is the max A64 can address, but needs total mainboard rerouting. At this stage TERES1 would never be developer laptop which you can use to build Linux kernels, or do fancy graphics etc. We see it more like hacker tool. We made it lightweight, our target is to run on battery for long time, so you can get it while you travel. We work on FPGA internal board which you will be able to program with FOSS and to add Oscilloscope and Logic Analyzer capability at later stage while keeping all other hardware intact so it will be add-on board. We think of TERES1 as to become portable lab for hackers, to may program Arduino boards, sniff protocols at hardware level, capture analogue signals etc. it will be still good to browse internet, edit text files, code embedded software, but do not expect it to replace your desktop.
Good suggestion was to bring out the debug UART console so developer could see kernel messages without opening the laptop and solder wires. So we decided to add multiplexer and will bring Serial UART TX, RX, GND on the audio headphone jack which will be multiplexed by software, so the developers could just plug serial cable to Audio jack and debug.
Some people suggested us to place Arduino connectors near the touchpad where you add Arduino shields, this need a bit of consideration. When you do prototype work and experiments there is always possibility to damage your hardware, even now when we use Arduino we always put USB-ISO between it and the computer we use to program. With this protection we are sure that if we short something or feed high voltage to the shield by accident we will not damage our computer. So this is great idea but needs a bit of thinking.
Some people were asking: “do you think if this will be commercial success project, your laptop is so expensive, there are Chinese laptops for $50, $60, $100?”
Frankly we do not care too much about this, our core business is development boards and if you follow our blog you see that we have enough work. We spend more than year on TERES I so far and it was fun project and we learned a lot during the development. Now if it will be liked by many people or not is not so important, the important thing is that we made first step to bring to people, who appreciate open source an platform and template which they can use and improve both harware and software wise.
This is why we selected KiCAD as our CAD for designing TERES I. What is the point to release OSHW made with Altium or Eagle which will require your community to spend thousands of EUROs if want to study or modify your files? Every time you use proprietary tool to make Open Source you just decrease your community base just to people who can afford to buy the tools you used to design.
Now TERES I gives freedom to everyone to download KiCAD, the CAD files from GitHub and people can view how it’s done, learn something new, and if you do not like something you can modify it up to your taste. You can’t do with any other laptop on the market.
Note that this is just the first step, the development and the fun will continue. Once we finish the software, add on boards we will look around for more new SOC candidates as well.
Not at least everyone was asking “when it will be available for sale?”. We build our first three prototypes 3 days before FOSDEM. While we worked more than year on the harware and we solved all issues there, the software is in quite initial state.
For the moment the only working Linux Kernel which supports all A64 features is the Allwinner Android Kernel. This Kernel is full of binary blobs, but the only one which could be used for demo. Beside the binary blobs many other things are broken, like the power management, different drivers like the LCD backlight PWM, wake up from suspend, eDP converter is not set properly and works just in 15 bit color mode etc etc. We have the hardware for 50 laptops ready (developer edition), but we do not want to ship before we take care for the software. At other hand we do not want to ship TERES I with Android or RemixOS also which are complete with binary blobs and will never be Open Source.
So let’s hope we will have good enough Linux support in couple of months and we can start the shipments, until then please wait patiently, we spend over an year and now we are close to the final 🙂
All above suggestions requiring the hardware modifications for the debug console, OTP lock, SPI Flash will be implemented in the next run when the software is completed.
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