Allwinner plans to release Linux capable RISC-V SOC this year

Searching for more info about their new H313 SOC I found old news from August 2020, where Allwinner announce the development of AP SOC with RISC-V and praising Open Source Hardware and the open ISA of RISC-V.

They say in this announcement that they will have AP (application processor) SOC with RISC-V in 2021!

There is lot of development around RISC-V in the last years. Espressif have their ESP32-C3 which is with RISC-V SOC, but it can’t run Linux as has not enough memory and video. We still can’t see affordable silicon capable to run Linux.

There is announcement for BeagleBoneV but still not in production and at quite higher price compared to ARM boards on the market.

Allwinner is known to be able to design and produce low cost SOCs. Let’s hope the semiconductor crisis caused by Covid19 will not delay their plans.

So is the year 2021 when we will see $35 Linux running boards with RISC-V?

I’m crossing fingers!

As soon as we can get our hands to these SOC we will make OSHW OLinuXino with it!

OSHW design and affordable SOC will lead to affordable boards and boost of the software development of RISC-V too.

Source: Allwinner news.

Hello RISC-V! We got samples of the new ESP32-C3 module and it is only 13×17 mm

We got some engineering samples of ESP32-C3 modules.

They are smaller than ESP32-WROOM and WROVER and measure just 17x13x2.5 mm!

This is the first Espressif product with RISC-V core, the datasheet is on their web.

This is also the first SOC with RISC-V core we have access to, so we are excited to learn more the ISA on low level.

Any resources to recommend? Is there something like small disassembler/monitor with few commands like read/write to memory and list code, which to allow you to write in assembly and run code?

Found this on GitHub today https://github.com/andportnoy/riscv-disassembler