myNetPCB – simple Open Source Schematic drawing program – Made in Bulgaria

myNETPCB

I got interesting request yesterday – we keep on our web long list with different CAD tools for PCB schematic design and layout.

Sergey Iliev asked me to add to the list the CAD program he works on last 4 years. The project is open source written in Java and hosted at SourceForge (yes this site is still live and kicking 🙂 )

He said he is working now on the PCB layout accompany program.

What impress me is that the package is only 600K Zip file.

A10-OLinuXino preliminary schematic uploaded on GitHub and we are open for discussions

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The A10-OLinuXino preliminary schematic is ready and we are open for discussions, the CAD files are just uploaded on GitHub so you can download and review.

Our aim was not to design yet another cheap tablet or A10 TV dongle reference design, but the most sophisticated and hackable, completely open source hardware and software development platform for A10. Board which will allow you to explore and employ all A10 features. With over 100 GPIOs, many SPI, I2C, UART, USB etc you got actually all interfaces you could think of except PCIe 🙂

What we put on the board:
– A10 Cortex A8 processor running at 1Ghz
– 1GB of DDR3 memory (organized as 4 x 256MB x8 with 2Gbit chips)
– 4GB NAND Flash
– HDMI
– VGA
– RS232 UART
– 100Mbit Ethernet
– LCD
– 2 USB hosts
– 1 USB OTG
– SATA
– JTAG
– UEXT1 and UEXT2 for connecting addtional UEXT modules like Zigbee, Bluetooth, Relays, etc
– GPIO-1,2,3,4 with total 132 GPIOs available for the user
– Audio Output, Audio Input, Line Input
– 7 buttons for android navigation
– status LED
– micro-SDcard
– normal size SD/MMC card
– 6-16VDC input power supply, noise immune design
– LiPo battery power option
– RESET and Power-Down buttons
– console debug UART port

The CAD files, PDF of the schematic and image of the BRD is at GitHub https://github.com/OLIMEX/OLINUXINO/tree/master/HARDWARE/A10-OLinuXino

Looking forward to hear your feedback 🙂

Note that the schematic and board are not complete so if you ask what the price would be we still really do not know for sure, what we target is to release this board for about EUR 60 retail and EUR 48 OEM (50+ pcs order) but these figures are preliminary and may go up down during the development.

A13-OLinuXino preliminary schematic is complete

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A13-OLinuXino preliminary schematic is complete, here is what we got:

– A13 Cortex A8 processor running at 1GHz
– MALI 400 GPU, 1080p codec
– 512 MB of RAM
– 3+1 HS USB hosts (one reserved for WIFI module on board)
– USB OTG (can power the board)
– Audio input
– Headphone output
– VGA connector
– (optional 4GB NAND flash on board)
– micro SDcard
– 6-16VDC power supply input
– (optional LiPo battery power supply block, allow board to run hours on LiPo 3.7V battery)
– (optional RTL8188CU WIFI module on board)
– 5 buttons
– Real Time Clock module with PCF8563
– LCD expansion port, if no connected to LCD provide 30 GPIOs
– UEXT connector with SPI, I2C, UART for attaching additional UEXT modules
– GPIO connector with 40 GPIOs
– console UART header for USB-SERIAL-CABLE console debug

The readable PDF version of the schematic is push on GitHub. CAD files will not be uploaded until we complete and debug the design.

We try to put this in 120×90 mm board size and this picture show preliminary attempt to put the connectors on correct locations.

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when we released iMX233 everyone was comparing this ARM9 board with Raspberry Pi or Beagle Bone, commenting how small memory it have and runs on only 454Mhz.

Now if we have to do same comparison and if we trust what is written here: http://lists.phcomp.co.uk/pipermail/arm-netbook/2012-June/004194.html i.e. that Cortex-A8 + NEON coprocessor at 500Mhz runs applications x4 times faster than ARM1176 at 720Mhz we have to say thay A13-OLinuXino will have x2 times more memory than RaspberryPi and will run code x8 times faster.
If we compare A13-OLinuXino with BeagleBone it will have x4 times more memory and will run code about x1.5 times faster.

EDIT: 13.06.2012 PCB layout changed to 130×90 mm to fit all connectors and buttons:

Mouse traps in A13 reference schematic

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Yesterday we discovered that the reference A13 schematic we got have some mouse traps inside.

The DDR3 RAM ball assignments are shifted with +1, this means if A0 address signal is assigned as K3 on Hynix datasheet it’s labeled K4 on A13 “reference” design schematic.

I still don’t know if this is intentional or not.

As explained on this tread http://lists.phcomp.co.uk/pipermail/arm-netbook/2012-March/002881.html the factories in China which produce electronic devices have no or little R&D, they rely on the SoC manufacturer to provide them with chips, schematics, reference PCB layout and everything they need just to start production, so they just pay for the design to “solution companies” and do what they can best – assembly cheap devices.

There may be other traps as well, but this will not stop us to complete our schematic, my great worries now are if the processor pin assignments are correct in the A13 datasheet 🙂 as we have nothing to compare with.

I already ordered one A13 tablet from China as these are still not available on ebay, so we will be able to do some reverse engineering and track if all ports on the A13 are defined correctly but this will delay a bit the project.

Hopefully I will got the A13 tablet next week and will tear it on parts, then post my findings here 🙂

I already wrote note in the GitHub A13-PDF readme.txt about this problem with the schematic so other people who watch this project beware.