Allwinner announced A20 processor as drop-in replacement for A10 designs, i.e. you could re-use your A10 board design for the new A20 processors which offer dual core power.
We already blogged that we got preliminary info and schematic to evaluate and last two days our developers were busy to compare the schematic info (as there is no datasheet for A20 yet).
Most of the GPIO ports on A20 match A10 ports, just some ports in A20 now have more functions but keep the old port functionality as well.
Well done Allwinner!
We spot some balls that are with differnt functionality though:
ball.A19 A20.TWI4_CLK A10.GPS_MAG ball.A20 A20.TWI3_CLK A10.GPS_CLK ball.B20 A20.TWI3_SDA A10.GPS_SIGN
these three are minor changes, we do not use GPS signals on board and they go to GPIO connector so no problem
another difference is on these two balls:
ball.R14 A20.NC A10.VREGIO_HDMI ball.R16 A20.NC A10.PLLREGIO
these two balls are left not connected on our A10 design too, so no problem
there are some differences in the PIO power supply:
ball.H10 A20 connected to 3V A10 connected to 3.3V ball.J10 A20 connected to 3V A10 connected to 3.3V
these two balls are connected to 3V in A20 schematic and to 3.3V to A10 schematic, we have to investigate this further!
the major differences between A10 and A20 are in the DDR3 wiring:
ball.N3 A20.SCKE A10.SCKE0 ball.J3 A20.SCK1# A10.ODT1 ball.J4 A20.SCK1 A10.SCKE1 ball.AA4 A20.A15 A10.SCS1
A10 have two chip-select one clock and two clock enables (second is not used in our schematic) and addresses up to A14
A20 have one clock enable with two pairs of clocks (one not wired on the A20 reference schematic) and addresses up to A15
so both chips can address up to 2GB RAM but in different way.
We didn’t complete our A10 schematic this info comes right on time, so we can make our schematic compatible with both A10 and A20 and to may support up to 2GB RAM
Conclusion: YES, it’s possible to design board which to may work with both A10 and A20, but not if you have not received the A20 info when you made your A10 board 🙂Â
olimex 
Apr 06, 2013 @ 17:12:58
Did A10 officially support 2GB RAM? I know it works, but I’m not sure it was officially supported. Would you have been ok in a 1GB system?
Apr 10, 2013 @ 11:42:16
What about sata, is it also on the A20 ?
Apr 10, 2013 @ 13:53:36
I’m not sure about this, the 2 pages flyer we got have no SATA at all, so they may have decided to drop it in A20
Apr 10, 2013 @ 15:13:01
Allwinner confirmed A20 have SATA 🙂
Apr 10, 2013 @ 16:16:47
Good to hear that… I was afraid it would be missing….
A20 looks very good successor then for the A10…
Apr 13, 2013 @ 19:06:13
Indeed it has SATA, marsboard is out: http://www.hotmcu.com/marsboard-a20-dev-board-p-60.html?cPath=33
Jun 08, 2013 @ 15:35:25
where can I find reference schematic and layout? which version of orcad tool I need to use to open it?
Jun 11, 2013 @ 02:07:36
Schematics for the Olimex A10/A20 OLinuXino MICRO board can be found at https://github.com/OLIMEX/OLINUXINO/tree/master/HARDWARE/A10-OLinuXino-MICRO
For reference schematics etc see http://linux-sunxi.org/A20 External Links section.
Jun 11, 2013 @ 16:07:27
Hi Henrik
Thanks for sharing good enfo. I have tried to open schematic and board file using different tools but I am not able open it. Do you know which pcb tool and version I need to se to open it. Thanks again for your help.
Jun 19, 2013 @ 18:06:11
Hi,
I don’t understand which change you had need to do because :
ball.N3 A20.SCKE A10.SCKE0 // Nothing change, it’s the same thing, right ?
ball.J3 A20.SCK1# A10.ODT1 // Unused on A10 and on A20
ball.J4 A20.SCK1 A10.SCKE1 // Unused on A10 and on A20
ball.AA4 A20.A15 A10.SCS1 // If you address up to A14 nothing change, right ?
Vivien
Jan 30, 2019 @ 18:07:42
Hi,
and what about DDR data lines?
A20: SDQ0 is on pin AC7
A10: SDQ0 is on pin AB4
and other data lines…
Can it be configurable on software?
Filipe