Our first attempt to route DDR memory at 2 layers in iMX233-OLinuXino-Mini didn’t went very well as we wanted to put all components on one layer thus to make manufacturing with single reflow for lower cost.
Unfortunately the board didn’t work reliable at higher than 64 Mhz DDR data bus clock as with the 2 layers design we couldn’t make all signals lenght same, but split it on two groups, anyway. We decided on iMX233-OLinuXino-Micro to try again 2 layer design but this time to put the DDR memory under the iMX233 chip and to make signal paths not even but very short. After all this is just 133Mhz not 1333Mhz as it will be on A10-OLinuXino
We routed the board and run prototypes which got assembled on 23th of May 16.00 oclock, so we could’t test them until today due to our Holidays.
Today we run the tests and board works great at 133Mhz DDR clock.
First the board was designed with USB-mini connector for taking 5V power supply, then I told our developers to change it to standard power supply barrel jack, but they didn’t understood correctly nor I have double check the PCB files before we ran the prototypes, so now first prototypes have USB-B connector for power supply :D, don’t worry it will be fixed in the production run, which is to follow. Also these prototypes were produced in Green color instead Red as they will be in production.
The CAD files of this working 2 layers design are uploaded on GitHub.
We are about to run few other tests tomorrow and put this board on tail for mass production. This means we will have these boards in stock about end of June (or earlier ).